This section is intended to provide information relevant to understanding the various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, the switching behavior of a transistor, such as, e.g., a metal-oxide-semiconductor field effect transistor (MOSFET), is affected by the parasitic capacitances between the device's three terminals, that is, gate-to-source (CGS), gate-to-drain (CGD) and drain-to-source (CDS) capacitances. These capacitance values are non-linear and a function of the device structure, geometry, and bias voltages. The capacitances come from a series combination of a bias independent oxide capacitance and a bias dependent depletion (Silicon) capacitance. Also, the input capacitance (CGD+CGS) may decrease with increasing voltage at shorted drain/source terminals due to a decrease in depletion capacitance, as voltage increases and the depletion region widens. Also, the lower the input capacitance, the faster the switching speed.